ashish

Faculty


Office Address


Qualification



Teaching & Research Experience


Research Interests


Roles and Responsibilities

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Information




Web Link

Publications


  • Office of IIIT Kota, 2nd Floor Prabha Bhawan, MNIT Jaipur Campus,
    JLN Marg, Jaipur - 302017, Rajasthan

  • Ph.D. Thesis Submitted (MNIT Jaipur)
  • M.Tech (MNIT Jaipur)
  • B.E (Govt. Engineering College Bikaner)

  • IIIT Kota - Faculty in CSE (June 2018 - till now)
  • Previous experience: 12+ years

  • Computer Architecture, Reliability-Aware Design,
  • Hardware Security, IoTs, AI and Machine Learning

  • Convener, Training & Placement Cell

  • Embedded System Design and Applications Course(FITT - IIT Delhi)
  • Fellowship Awarded for Embedded System Week 2014
  • Fellowship Awarded for VLSI Design in 2015, 2016.
  • Fellowship Awarded for VDATE in 2015, 2016 and 2018


  • Google citation link

  • Book
  • Embedded System Design by Ashish Sharma & Bhavna Mahure – Neelkanth Publishers (P) LTD, 7 Feb 2011.
  • Journals
  • 1. N. Gupta, A. Sharma, V. Laxmi, M. S. Gaur, M. Zwolinski and R. Bishnoi, "LBDR: generic congestion handling routing implementation for two-dimensional mesh network-on-chip," in ​ IET Computers & Digital Techniques , ​ vol​ . 10, no. 5, pp. 226-232, 9 2016.
  • 2. Sharma Ashish, Sumit Srivastava “An Alternative Approach to Two Phase Encryption using Back-Propagation Feed Forward Neural Technique” International Journal of Computational Intelligence Research (IJCIR) 2010.​ ISSN 0973-1873 Volume 6, Number 3 (2010), pp. 333–342.
  • Conferences
  • 1. Sharma Ashish, Shivani Yadav, Neeraj Yadav “PID ​ Controller with Distributed P, I, D Actions for Linear and Non-Linear Plants​ ” International Conference ​ ICACTEA​ , 2011.
  • 2. Ashish Sharma, Sandhya Chandravanshi , Vatsala Sharma “Design and Implementation of high speed multipliers” National Symposium on “​ Microelectronics and System (NSMS 2012) “organized by Department of Electronics, School of Physical Sciences, Banasthali University, Rajasthan.(Awarded By Best Paper of Symposium).
  • 3. Ashish Sharma, Manoj Singh Gaur, Lava Bhargava, Vijay Laxmi, and Mark Zwolinski, “Hiper-nirgam: A tool chain based framework for modeling thermal-aware reliability estimation in 2d mesh nocs”, in ​ DATE 2015 University Booth, 2015.
  • 4. Ashish Sharma, Prachi Upadhyay, Ruby Ansar, Vijay Laxmi, Lava Bhargava, Manoj Singh Gaur, and Mark Zwolinski, “A framework for thermal aware reliability estimation in 2d noc”, in VLSI Design and Test (VDAT), 2015 19th International Symposium on. IEEE, 2015, pp. 1–6.
  • 5. Ruby Ansar, Prachi Upadhyay, Manish Singhal, Ashish Sharma, and Manoj Singh Gaur, “Characterizing impacts of multi-vt routers on power and reliability of network-on-chip”, in Contemporary Computing (IC3), 2015 Eighth International Conference on. IEEE, 2015, pp. 476–480.
  • 6. Niyati Gupta, Manoj Kumar, Ashish Sharma, Manoj Singh Gaur, Vijay Laxmi, Masoud Daneshtalab, and Masoumeh Ebrahimi. 2015. Improved Route Selection Approaches using Q-learning framework for 2D NoCs. In ​ Proceedings of the 3rd International Workshop on Many-core Embedded Systems (MES '15). ACM, New York, NY, USA, 33-40.
  • 7. M. S. Gaur, V. Laxmi, M. Zwolinski, M. Kumar, N. Gupta and Ashish, "Network-on-chip: Current issues and challenges," ​ VLSI Design and Test (VDAT), 2015 19th International Symposium on ​ ,Ahmedabad, 2015, pp. 1-3.
  • 8. Ashish Sharma, Ruby Ansar, Manoj Singh Gaur, Lava Bhargava, Vijay Laxmi “Reducing FIFO Buffer Power Using Architectural Alternatives at RTL”, in VLSI Design and Test (VDAT), 2016 20​ th ​ International Symposium on. IEEE, 2015, pp. 1–6.